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Mocus Algorithm for obtaining Minimal cut set (Mcs) of a random computer network system

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 زاهر عبد الهادي حسن الشنون
31/01/2020 18:05:55
تصفح هذه الورقة الالكترونية بتقنية Media To Flash Paper
Zahir Al Shanoon, [31.01.20 20:51]
Fault Tree and Success Tree Methods:
The operation of a system can be considered from two opposite viewpoints: the various ways that a system fails or the various ways that a system succeeds. Most of the construction and analysis methods used are, in principle, the same for both fault trees and success trees. First we will discuss the fault tree method and then describe the success tree method.
1- Fault Tree Analysis (FTA)
This method was developed at the Bell Laboratories in the early
1960s to evaluate the reliability and safety of the Minuteman Launch
Control System [3]. Fault tree analysis (FTA) starts by defining the
undesirable state (event) of the system or item under consideration
and then analyzes the system to determine all possible situations
that can result in the occurrence of the undesirable event. Thus, it
identifies all possible failure causes at all possible levels associated
with a system as well as the relationship between causes. FTA can
be used to analyze various types of maintainability-related problems. FTA uses various types of symbols [3]. Four commonly used symbols in fault tree construction are shown in Figure 2. The circle denotes a basic fault event or the failure of an elementary component. The event s occurrence probability and failure and repair rates are normally obtained from empirical data. The rectangle denotes a
fault event that results from the combination of fault events through
the input of a logic gate.
Figure 2: Four commonly used fault tree symbols: (a) AND gate,
(b) OR gate, (c) rectangle and (d) circle.
The OR gate denotes that an output fault occurs if one or more
of the input fault events occur. Finally, the AND gate denotes that
an output fault event occurs only if all the input fault events occur.
The probabilities of the occurrence of the output fault events of logic
gates (OR and AND) are given by
The OR gate
??(??0)=1??1???(????????=1) (1)
where ??(??0) is the probability of occurrence of the OR gate output
fault event, ??0 , n is the number of independent input fault events,
and ??(????) is the probability of occurrence of input fault event ????
for i = 1, 2, 3, . . . , n .
The AND gate
??(??0)=???(????????=1) (2)
where ??(??0) is the probability of occurrence of the AND gate
output fault event, ??0 and ??(????) is the probability of occurrence
of input fault event ???? for i = 1, 2, 3, . . . , n.
Figure 3: a fault tree of a random computer network system
By using Boolean algebra operations we get : T=E1.E2.E3
E13=X8+X12, E12=X9.E13=X8X9+X9X12 E3=X3+E12= X3+X8X9+X9X12 (3) E11=X8+X12, E10=X9.E11=X8X9+X9X12
E8=X6+E10=X6+X8X9+X9X12, E9=X7+X11
E2=X2+E7=X2+X6X7+X7X8X9+X7X9X12+X6X11+X8X9X11+X9X11X12 (4)
E6=X5+X11, E5=X4+X10
E1=X1+E4=X1+X4X5+X4X11+X5X10+X10X11 (5)
From 3,4 and 5 we get :
T=x1x2x3 + x2x3x4x5 + x1x3x6x7 + x1x2x8x9 + x2x3x4x11 + x2x3x5x10 + x1x3x6x11 + x1x2x9x12 + x3x4x6x11 + x1x7x8x9 + x2x3x10x11 + x1x7x9x12 + x1x8x9x11 + x3x6x10x11 + x4x8x9x11 + x1x9x11x12 + x4x9x11x12 + x8x9x10x11 + x9x10x11x12 + x3x4x5x6x7 + x2x4x5x8x9 + x3x5x6x7x10 + x2x4x5x9x12 + x4x5x7x8x9 + x2x5x8x9x10 + x4x5x7x9x12 + x4x5x8x9x11 + x2x5x9x10x12 + x5x7x8x9x10
the all minimal cut sets of the system are
{x1,x2,x3}, {x2,x3,x4,x5}, {x1,x3,x6,x7},{x1,x2,x8,x9}, {x2,x3,x4,x11},
{x2,x3,x5,x10 },{x1,x3,x6,x11},{ x1,x2,x9,x12}, {x3,x4,x6,x11}, {x1,x7,x8,x9},
Figure 4: Parallel- series system structure
The Reliability of a parallel-series system is
????= ?(1??(1?????)) (6)????=1????=1

Zahir Al Shanoon, [31.01.20 20:51]
????= R3R9 + R1R4R10 + R1R5R11 + R2R6R9 + R2R7R11 + R3R8R12 - R2R3R6R9 + R2R6R8R12 - R3R8R9R12 - R1R2R5R7R11 - R1R3R4R9R10 - R1R3R5R9R11 - R1R4R5R10R11 - R2R3R6R8R12 - R2R3R7R9R11 - R2R6R7R9R11 - R2R6R8R9R12 - R1R2R4R6R9R10 - R1R2R5R6R9R11 - R1R2R4R7R10R11 - R1R3R4R8R10R12 + R2R3R6R7R9R11 - R1R3R5R8R11R12 + R2R3R6R8R9R12 - R2R3R7R8R11R12 - R2R6R7R8R11R12 + R1R2R3R4R6R9R10 + R1R2R3R5R6R9R11 + R1R2R3R5R7R9R11 + R1R2R4R5R7R10R11 + R1R2R5R6R7R9R11 - R1R2R4R6R8R10R12 + R1R3R4R5R9R10R11 - R1R2R5R6R8R11R12 + R1R3R4R8R9R10R12 + R1R3R5R8R9R11R12 + R2R3R6R7R8R11R12 + R2R3R7R8R9R11R12 + R2R6R7R8R9R11R12 - R1R2R3R5R6R7R9R11 + R1R2R3R4R6R8R10R12 + R1R2R3R4R7R9R10R11 + R1R2R3R5R6R8R11R12 + R1R2R4R5R6R9R10R11 + R1R2R3R5R7R8R11R12 + R1R2R4R6R7R9R10R11 + R1R2R4R6R8R9R10R12 + R1R2R5R6R7R8R11R12 + R1R2R5R6R8R9R11R12 + R1R3R4R5R8R10R11R12 - R2R3R6R7R8R9R11R12 - R1R2R3R4R5R6R9R10R11 - R1R2R3R4R5R7R9R10R11 - R1R2R3R4R6R7R9R10R11 - R1R2R3R4R6R8R9R10R12 - R1R2R3R5R6R7R8R11R12 - R1R2R4R5R6R7R9R10R11 - R1R2R3R5R6R8R9R11R12 + R1R2R3R4R7R8R10R11R12 - R1R2R3R5R7R8R9R11R12 + R1R2R4R5R6R8R10R11R12 + R1R2R4R6R7R8R10R11R12 - R1R2R5R6R7R8R9R11R12 - R1R3R4R5R8R9R10R11R12 + R1R2R3R4R5R6R7R9R10R11 - R1R2R3R4R5R6R8R10R11R12 - R1R2R3R4R5R7R8R10R11R12 - R1R2R3R4R6R7R8R10R11R12 + R1R2R3R5R6R7R8R9R11R12 - R1R2R4R5R6R7R8R10R11R12 - R1R2R3R4R7R8R9R10R11R12 - R1R2R4R5R6R8R9R10R11R12 - R1R2R4R6R7R8R9R10R11R12 + R1R2R3R4R5R6R7R8R10R11R12 + R1R2R3R4R5R6R8R9R10R11R12 + R1R2R3R4R5R7R8R9R10R11R12 + R1R2R3R4R6R7R8R9R10R11R12 + R1R2R4R5R6R7R8R9R10R11R12 - R1R2R3R4R5R6R7R8R9R10R11R12
2-Success Tree Analysis (STA)
The success tree method is conceptually the same as the fault tree method. By defining the desirable top event, all intermediate and primary events that guarantee the occurrence of this desirable event are deductively postulated. Therefore, if the logical complement of the top event of a fault tree is used as the top event of a success tree, the Boolean structure represented by the fault tree is the Boolean complement of the success tree. Thus, the success tree, which shows the various combinations of success events that guarantee the occurrence of the top event, can be logically represented by path sets instead of cut sets. to better understand this problem, consider a random computer network shown in Figure 1. The success tree for this system is shown in Figure 5.
Figure 5: a success tree of a random computer network system
By Using Boolean algebra operations, we get:
E13=X8X12, E12=X9+ E13=X9+X8X12
E3=X3E12=X3X9+X3X8X12 (7)
E11=X8X9, E10=X9+X8X12
E8=X6.E10=X6X9+X6X8X12, E9=X7X11
E2=X2E7=X2X7X11+X2X6X9+X2X6X8X12 (8)
E6=X5X11, E5=X4X10
E1=X1E4=X1X4X10+X1X5X11 (9)
from 7,8 and 9 we get:
T= X1X4X10+X1X5X11+X2X7X11+X2X6X9+X2X6X8X12+X3X9+X3X8X12
The all minimal path sets of the system are {x1,x4,x10}, {x1,x5,x11}, {x2,x7,x11}, {x2,x6,x9},{x2,x6,x8,x12},{x3,x9},{x3,x8,x12}
Figure 6: series - Parallel system structure
The reliability of a series-parallel system is
????= 1??(1??????) (10)????=1????=1

  • وصف الــ Tags لهذا الموضوع
  • reliability network; Fault Tree Analysis; MOCUS Algorithem; Minimal cut set