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CASCADED COUNTERS

الكلية كلية الهندسة     القسم  الهندسة الكهربائية     المرحلة 4
أستاذ المادة ايهاب عبد الرزاق حسين محمد       16/12/2016 19:12:08
CASCADED COUNTERS

Counter circuits can be cascaded to increase both the modulus of the count sequence and the frequency division. Large counter applications requiring several stages of cascaded counters include digital time clocks, frequency dividers, and synchronization circuits. The simplest example of cascaded counter stages is an asynchronous counter. The individual toggle flip-flop stages of an asynchronous counter are MOD-2 counters. MOD-2 counters are cascaded by routing the output of one stage into the clock input of the next stage. With each cascaded stage, the modulus of the counter increases. The final modulus of the counter is equal to the modulus of the individual stages multiplied together. Thus, a 4-bit asynchronous counter has a modulus of 2x2x2x2=16. The output frequency from the final stage is equal to the input frequency divided by the modulus. A simplified block diagram of the cascaded counter stages is shown in Figure (29). The input clock frequency is divided by 2 at each stage.

The 74LS90 IC counter is an example of a counter circuit that requires cascading in order to obtain a decade counter. The decade counter is formed by cascading a MOD-2 counter with a MOD-5 counter. The final modulus is 2x5, or 10.

Several 74LS90 counters could be cascaded together to obtain MOD-10,
MOD-100, and MOD-1000 counters. The most significant output bit, QD, is used as the
cascaded clock input to the next stage; Figure () shows a simplified block diagram of
MOD-10 counters cascaded together.


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