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# SYNCHRONOUS COUNTERS ANALYSIS AND DESIGN

الكلية كلية الهندسة     القسم  الهندسة الكهربائية     المرحلة 4
أستاذ المادة ايهاب عبد الرزاق حسين محمد       16/12/2016 18:51:58
SYNCHRONOUS COUNTERS
Synchronous digital counters have a common clock signal that controls all flip-flop stages. Since a common clock controls all flip-flops simultaneously, there are no cumulative delays that result when a clock signal must ripple through the stages, as in the case of asynchronous counters. Synchronous counters can count up and down, and can be designed to produce special purpose count sequences of nonconsecutive numbers.
Synchronous Counter Analysis
Synchronous counters can be analyzed by using a procedure similar to the analysis of asynchronous counters to classify fully or define the counter operation.
Analyze a synchronous counter circuit by proceeding through the following steps:
1. Verify that the counter system clock is common to all flip-flop stages and that the circuit is in fact a synchronous counter.
2. Determine the number of stages of the counter by counting the flip-flops or outputs.
3. Determine the type of flip-flops and the input logic function for each stage. For reference, recall the present state-present input-next state table for each flip-flop.
4. Construct a present input-present state-next state table for the counter to determine the inputs to the flip-flops and the resulting outputs.
5. Analyze the counter using the present input-present state-next state table to determine the complete count sequence. Continue the analysis until the count sequence begins to repeat.
6. Determine the modulus of the counter.
7. Construct a state transition diagram to describe the counter operation.
8. Graph the output waveforms produced by the counter. The key to the synchronous counter analysis is the present state-present input-next state table that serves as a truth table description of the counter operation as it progresses with each clock pulse. To complete this table properly, we need to define correctly the flip-flops of each stage by their own present input-present state-next state table.
EXAMPLE (12): Synchronous Counter Analysis Problem:
Analyze the counter circuit shown in Figure (16).
Solution:
The circuit in Figure (16) is a three-stage synchronous counter since a common clock signal controls all three J-K flip-flop stages of the counter. The J-K flip-flop operation is defined in Table (l). The present input-present state-next table describing the counter operation is constructed with the initial present state of the flip-flops assumed to be a logic LOW. The J and K inputs can be specified according to their logic equations: Present states: QC, QB, QA= 0, 0, 0.

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