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ASYNCHRONOUS COUNTER ANALYSIS AND DESIGN

الكلية كلية الهندسة     القسم  الهندسة الكهربائية     المرحلة 4
أستاذ المادة ايهاب عبد الرزاق حسين محمد       16/12/2016 18:47:50
ASYNCHRONOUS COUNTER CIRCUITS
Asynchronous counters do not have a common clock that controls all the Hip-flop stages. The control clock is input into the first stage, or the LSB stage of the counter. The clock for each subsequent stage is obtained from the output from the prior flip-flop stage. Toggle flip-flops are used almost exclusively in the design of asynchronous counters. With the toggle flip-flop, the output state toggles between a logic HIGH and a logic LOW on each clock pulse. The external clock that controls the flip-flop output state is input into the LSB stage. Either the true or inverted output from the flip-flop can serve as the output bit value to form the count state or as the clock to the next stage in the counter circuit. For any given asynchronous counter circuit, the count direction for counting serially up or down is dependent on the triggering of the flip-flops. An asynchronous counter designed for positive edge-triggered flip-flops will not generate the desired count sequence if negative edge-triggered flip-flops are substituted in the circuit design. Analyzing waveforms into and out of the flip-flops is crucial to obtaining a properly functioning circuit. Asynchronous counters often experience many timing and glitch problems due to the cumulative propagation delays resulting from the clock ripple action through the flip-flop stages. The effects of the delays worsen with increased counter size and limit the input clock rate. The design procedures for asynchronous serial counters are relatively simple. Techniques for analyzing the operation and designing asynchronous counters are the subject of the next sections.
Asynchronous Counter Analysis
Asynchronous counter analysis is carried out according to the procedures specified in above. A detailed procedure to follow for analyzing asynchronous counters is demonstrated in Examples (8 and 9).
EXAMPLE (8): Asynchronous Counter Analysis Problem: Analyze the operation of the counter in Figure (4). Solution: By observing the circuit in Figure (4), it can be seen that it is a 4-bit positive edge-triggered asynchronous counter. Begin the waveform analysis by drawing an input clock waveform Assume a 50% duty cycle unless otherwise known. Then graph the output waveforms from each flip-flop stage of the counter. Note that only the LSB stage is triggered by the input clock; all other stages are triggered by an output from the previous stage. The waveforms are shown in Figure (8). The state transition diagram, derived from the waveforms, is shown in Figure (9).
The counter classification is completed by summarizing the characteristics displayed in the state transition diagram:
• MOD 16.
• Divide by 16.
• Asynchronous.
• Four-bit.
• Positive edge-triggered.
• Binary down counter.

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