معمارية: المحاضرة الرابعة - الكاش

Cache Memory
By Noor Kadhum

Historical introduction


Sir Maurice Vincent Wilkes
Principle of Locality of reference again

The idea behind using a cache as the first level of the memory hierarchy is to keep the information expected to be used more frequently by the CPU in the cache (a small high-speed memory that is near the CPU).
The end result is that at any given time some active portion of the main memory is duplicated in the cache. Therefore when the processor makes a request for a memory reference, the request is first sought in the cache. If the request corresponds to an element that is currently residing in the cache, we call that a cache hit. On the other hand, if the request corresponds to an element that is not currently in the cache, we call that a cache miss.

Important Laws:

1) Hit ratio = hit / (hit + miss)

2) access time cache = (hit + miss ) * t cache

3) access time M.M= miss * t M.M

4) Total access time = Access time cache + Access time M.M

5) Average access time :

a- with cache = Total access time / (hit+miss)
b- without cache = t M.M
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Example:
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Compute the Average access time for memory system when the time for M.M is 1000 ns, the time for cache is 100 ns and hit ratio is 0.9.

Sol:
Hit ratio = 0.9= 9/10 --> Hit =9 , miss =1
Access time cache = (hit + miss ) * t cache
= 10 * 100ns = 1000 ns
Access time M.M= miss * t M.M
= 1* 1000 ns = 1000 ns

Total access time = Access time cache + Access time M.M
= 1000 + 1000 = 2000 ns
Average access time :

a- with cache = Total access time / (hit+miss)
= 2000 ns / 10 = 200 ns
b- without cache = t M.M
= 1000 ns
Type of Cache memory

Cache memory, also called CPU memory, is random access memory (RAM) that a computer microprocessor can access more quickly than it can access regular RAM.Cache memory improves the speed of the CPU, but it is expensive. Type of Cache Memory is divided into different level that are L1,L2,L3:
Level 1 (L1) cache or Primary Cache
L1 is the primary type cache memory. The Size of the L1 cache very small comparison to others that is between 2KB to 64KB, it depent on computer processor.It is a embedded register in the computer microprocessor(CPU). The Instructions that are required by the CPU that are firstly searched in L1 Cache.
Level 2 (L2) cache or Secondary Cache
L2 is seconday type cache memory. The Size of the L2 cache is more capacious than L1 that is between 256KB to 512KB.L2 cache is Located on computer microprocessor. After searching the Instructions in L1 Cache, if not found then it searched into L2 cache by computer microprocessor. The high-speed system bus interconnecting the cache to the microprocessor.
Level 3 (L3) cache
Its is typically specialized memory that works to improve the performance of L1 and L2. It can be significantly slower than L1 or L2, but is usually double the speed of RAM. In the case of multicore processors, each core may have its own dedicated L1 and L2 cache, but share a common L3 cache. When an instruction is referenced in the L3 cache, it is typically elevated to a higher tier cache.


Cache-Mapping Function (Single cache model)

A request for accessing a memory element is made by the
processor through issuing the address of the requested element. The address issued by the processor may correspond to that of an element that exists currently in the cache (cache hit); otherwise, it may correspond to an element that is currently residing in the main memory.
Therefore, address translation has to be made in order to determine the whereabouts of the requested element. This is one of the functions performed by the memory management unit (MMU). A schematic of the address mapping function is shown in the following Figure:


In this figure, the system address represents the address issued by the processor for the requested element. This address is used by an address translation function inside the MMU. If address translation reveals that the issued address corresponds to an element currently residing in the cache, then the element will be made available to the processor.
If, on the other hand, the element is not currently in the cache, then it will be brought (as part of a block) from the main memory and placed in the cache and the element requested is made available to the processor.