الخطة التدريسية لمادة التصميم المنطقي

(( أستمارة الخطة التدريسية السنوية ))

Course Instructor Farah Mohammed Hassan Al-Sharefii
فرح محمد حسن الشريفي
E_mail Farahmh1982@yahoo.com
Title Logic Design
Course Coordinator

Course Objective
The objective of this course is to provide students some knowledge about digital computers and logic circuits, Our approach is to develop the ability of student to understand how the circuit represent the mathematical operation and how to prove the rules and laws of arithmetic operations by using it ,and how the digital system using discrete element of information

Course Description

*Logic design is concerned with the design of digital electronic circuits.digital circuit are employed in the design of systems such as digital computers, electronic calculators ,digital control devices ,digital communication equipment and many other application that required electronic digital hardware
*In this course we talking about the main characteristic of digital system which its manipulation of "discrete elements" of information .


Textbook
M.MORRIS MANO (2000) (Digital Design )

Thomas L. Floyd (Digital Fundamentals)

References
PAL Devices Data Book and Design Guide, Sunnyvale, Calif.: Advanced Micro Devices, 2006.

Programmable Logic Data Book, San Jose, Calif.: Cypress Semiconductors, 2000.


Course Assessment Term Tests Laboratory Quizzes Project Final Exam
As (25%) As (10%) As (05%) ---- As (60%)


General Notes

Study system : yearly




جدول الدروس الاسبوعي – الفصل الدراسي الاول

الملاحظات الماده العملية الماده النظرية التاريخ الاسبوع
Getting Started with circuit maker system Introduction to Logic Design and knowing the Numbering Systems
1
System Principles of circuit maker NumberBase Conversions, Complement 2
understand basic logic gates Boolean Function Representation, Canonical Form, Conversion between Canonical Forms
3
implement the basic gates by using circuit maker system Standard Form, Conversion between Standard and Canonical Forms 4
understand the work of NAND and NOR gates Boolean Functions implementation, Digital Logic Gates 5
implement NAND and NOR gates NAND and NOR Implementation, Simplification of Boolean functions (minimization) 6
implement Karnaugh Map with two variables The Map Method (Karnaugh Map), Two and Three Variables Map, FourVariables Map,
7
implement Karnaugh Map with three variables Karnaugh Map Simplification, (Pairs, Quads and Octets), Overlapping Group 8
First Exam 9
implement Karnaugh Map with four variables Adders , Half – Adder, Full- Adder 10
implement Adder Sub tractors, Half- Sub tractors, Full - Sub tractors 11
implement Half-Adder Code Conversion 12
implement Full-Adder Analysis Procedure 13
Implement Subtractors Multilevel NAND Circuits 14
Implement Full-Subtractors Multilevel NOR Circuits 15
Second Exam 16
عطلة نصف السنة



جدول الدروس الاسبوعي – الفصل الدراسي الثاني

الملاحظات الماده العملية الماده النظرية التاريخ الاسبوع
Implement Half-Sutractors Exclusive OR and Equivalence Functions 1
Implement Exclusive-OR
Relation between XOR and XNOR
2
Implement Exclusive-NOR
Combinational Logic With MSI and LSI 3

Implement Binary Parallel Adder Examples of Combinational Logic With MSI and LSI 4
Implement Binary Parallel Adder Binary parallel Adder 5
Implement Basic Flip-Flop Magnitude Comparator 6
Implement Basic Flip-Flop Examples of Magnitude Comparator 7
Third Exam 8
Implement Clocked RS-Flip Flop Decimal Adder 9
Implement Clocked RS-Flip Flop Decoders and Encoders 10
Implement D Flip-Flop Sequential Logic , Flip-Flops 11
Implement JK Flip-Flop Basic Flip- Flop Circuit, Clocked RS Flip-Flop 12
Implement T Flip-Flop D Flip- Flop, JK Flip-Flop, T Flip-Flop 13
Implement Master Slave Flip-Flop Master Slave Flip-Flop 14
Implement Triggering of Flip-Flop Triggering of Flip-Flop, Edge Trigger Flip – Flop 15
Fourth Exam 16

مدرس المادة وتوقيعه رئيس القسم وتوقيعه العميد وتوقيعه
مدرس مساعد/ فرح محمد حسن د. محمد عبد الله ناصر د. عبد الكريم البيرماني