Shared Memory Architecture-Part Two

Multiple copies of data, spread throughout the caches, lead to a coherence problem among the caches.
•The copies in the caches are coherent if they all equal the same value.
•However, if one of the processors writes over the value of one of the copies, then the copy becomes inconsistent because it no longer equals the value of the other copies.
•If data are allowed to become inconsistent (incoherent), incorrect results will be propagated through the system, leading to incorrect final results.
•Cache coherence algorithms are needed to maintain a level of consistency throughout the parallel system.
In a single cache system, coherence between memory and the cache is maintained using one of two policies:
1.write-through
2.write-back
•When a task running on a processor P requests the data in memory location X, for example, the contents of X are copied to the cache, where it is passed on to P.
•When P updates the value of X in the cache, the other copy in memory also needs to be updated in order to maintain consistency.
•In write-through, the memory is updated every time the cache is updated.
•in write-back, the memory is updated only when the block in the cache is being replaced.
In multiprocessing system, when a task running on processor P requests the data in global memory location X, for example, the contents of X are copied to processor P’s local cache, where it is passed on to P. Now, suppose processor Q also accesses X. What happens if Q wants to write a new value over the old value of X?
•There are two fundamental cache coherence policies:
(1) write-invalidate (2) write-update
•Write-invalidate maintains consistency by reading from local caches until a write occurs.
•When any processor updates the value of X through a write, posting a dirty bit for X invalidates all other copies.
•For example, processor Q invalidates all other copies of X when it writes a new value into its cache. This sets the dirty bit for X. Q can continue to change X without further notifications to other caches because Q has the only valid copy of X.