Write strategies of cache memory

Write Strategies
The problem: How to keep cache content and the content of main memory consistent without losing too much performance?
Problems arise when a write is issued to a memory address, and the content of the respective address is potentially changed.
• Write-through
All write operations are passed to main memory; if the addressed location is currently hold in the cache, the cache is updated so that it is coherent with the main memory. For writes, the processor always slows down to main memory speed.
• Write-back(Copy-back)
Write operations update only the cache memory which is not kept coherent with main memory; cache lines have to remember if they have been updated; if such a line is replaced from the cache,
its content has to be copied back to memory. good performance (usually several writes are performed on a cache line before it is replaced and has to be copied into main memory), complex
hardware.
Cache coherence problems are very complex and difficult to solve
in multiprocessor systems.